Timing control circuit for solid state protective relays for providing novel control of the pickup and timing circuits provided therein

ABSTRACT

A static relay having sensing, reference, pickup and timing circuits and comprising a novel timing control circuit. The pickup circuit functions to initiate operation of the timing circuit when a predetermined threshold level of overload conditions exist. The novel timing control circuit functions to prevent the timing circuit from being reset due to momentary dips below the aforesaid threshold level while providing means for rapid reset of the timing control circuit when the input being monitored remains below the threshold.

United States Patent 11 1 1111 3,792,313 Conrad 1 Feb. 12, 1974 [54]TIMING CONTROL CIRCUIT FOR SOLID 3,434,011 3/l969 Zocholl 317/36'11)STATE PROTECTIVE RELAYS FOR PROVIDING NOVEL CONTROL OF THE PICKUP ANDTIMING CIRCUITS PROVIDED THEREIN Inventor: Richard Conrad, Levittown,Pa.

Assignee: I-T-E Imperial Corporation,

Philadelphia, Pa.

Filed: Oct. 2, 1972 Appl. No.: 293,913

US. Cl. 317/27 R, 317/36 TD, 317/38, I 317/141 S Int. Cl. H02h 3/08Field of Search... 317/36 TD, 38, 27 R, 141 S, 317/49', 50; 307/141.4

References Cited UNITED STATES PATENTS 2/1972 Simpson 317/141 5 PrimaryExaminer--A. D. Pellinen Assistant Examiner-Harvey Fendelman Attorney,Agent, or Firm-Ostrolenk, Faber, Gerb & Soffen [57] ABSTRACT A staticrelay having sensing, reference, pickup and timing circuits andcomprising a novel timing control circuit. The pickup circuit functionsto initiate operation of the timing circuit when a predeterminedthreshold level of overload conditions exist. The novel timing controlcircuit functions to prevent the timing circuit from being reset due tomomentary dips below the aforesaid threshold level while providing meansfor rapid reset of the timing control circuit when the input beingmonitored remains below the threshold.

4 Claims, 2 Drawing Figures TIMING CONTROL CIRCUIT FOR SOLID STATEPROTECTIVE RELAYS FOR PROVIDING NOVEL CONTROL OF THE PICKUP AND TIMINGCIRCUITS PROVIDED THEREIN The present invention relates to a staticrelay and more particularly to a static relay employing a novel timingcontrol circuit between the pickup circuit and the inverse time delaycircuit to prevent reset of the inverse and time delay circuit due tomomentary dips ot" theeondition being monitored below a preset thresholdlevel, while at the same time providing means for rapid reset of thetiming control circuit when the condition being monitored remains belowthe threshold level.

BACKGROUND OF THE INVENTION The use of static relays in the field ofpower transmission and distribution has increased rapidly in recentyears due to the advantageous characteristics of such relays namelytheir solid state nature thereby eliminating any moving mechanical partsand their long useful operating life. One such typical design presentlyin use is described in US. Pat. No. 3,319,127, assigned to the assigneeof the present application. The static relay described therein isbasically comprised of a circuit for sensing the condition beingmonitored and converting same to a dc. level; a trip circuit foractivating protective equipment such as, for example, a circuit breaker;a timing circuit causing operation of the trip circuit in accordancewith an inverse time current relationship depending upon the magnitudeof the overload condition sensed; and a pickup circuit for initiatingoperation of the timing circuit only after the condition being monitoredpasses a predetermined threshold level. The desired characteristics ofsuch a static relay are such that the timing circuit must be maintainedat a reset or zero level condition when the condition being monitored isbelow the designated threshold level. Once the threshold level isachieved, however, the timing ele-. ment must be free to initiate itstiming operation without being influenced by the control of the pickupcircuit. As a further requirement, the timing circuit must be capable ofignoring or overriding momentary dips below the threshold level, whilebeing capable of resetting quickly if the input remains below thethreshold level. Since momentary dips below the threshold level willoccur at regular intervals due to the nature of the output of d.c.rectified circuits, it is conventional to employ filter circuits for thepurpose of smoothing and filtering the half or fullwave rectifiedsignals so as to eliminate such momentary dips. This techniquesignificantly increases the cost of the static relay and furthersignificantly decreases the single phase to three phase response of thecircuit and provides increased time lag in the sensing of the removal ofan overload condition.

BRIEF DESCRIPTION OF THE PRESENT INVENTION The present invention ischaracterized by providing a novel reset time delay circuit whichpermits the timing circuit to continue its timing function and therebyignore or override momentary dips in the condition being monitored belowthe designated threshold level, while at the same time providing rapidreset of the timing circuit when the condition being monitored remainsbelow the threshold level andwhich further provides good single phase tothree phase response without the need for filtering techniquesheretofore employed in conventional static relays.

It is therefore one object'of the present invention to provide a novelreset .time delay circuit for use in static relays and the like whichenables the timing element of the static relay to distinguish betweenmomentary dips below a designated threshold level of the condition beingmonitored and substantially lengthy drops below the threshold level soas to provide for positive as opposed to erratic operation of the staticrelay and permit the timing element to be rapidly reset during thoseinstances in which the condition being monitored remains below thedesignated threshold level.

BRIEF DESCRIPTION OF THE FIGURES The above as well as other objects ofthe present invention will become apparent when reading the accompanyingdescription and drawings in which:

FIG. 1 is a schematic diagram of a timing control circuit designed inaccordance with the principles of the present invention.

FIG. 2 shows a static relay structure employing a timing control circuitof the type shown in FIG. 1.

DETAILED DESCRIPTION OF THE FIGURES Summarizing the pertinentcharacteristics of a static relay such as, for example, protectiverelays of the overcurrent type, the necessary function is the control ofthe timing element. In response to inputs through the relay below adesignated threshold level, the timing element must be held in a resetor zero condition. In response to input levels above the thresholdlevel, the timing element must be released to allow a time delayinterval to begin. This time delay interval is a function of the designof the timing element and should not be influenced by the controlelement. However, if the input condition being monitored falls below thethreshold, operation of the timingelement must be terminated and thetiming element reset to the zero condition.

As a further requirement, the timing control must override the momentarydips in the condition being monitored below the threshold level and yetbe capable of resetting quickly when the input remains below thethreshold.

FIG. 1 shows a circuit 10 especially advantageous for use with solidstate overcurrent relays of the type employing resistor capacitor timingelements and exhibiting the function described hereinabove.

The circuit 10 of FIG. 1 provides four basic functions, namely;

1. Level detection (elements Z1 and R1);

2. Reset clamping (transistor Q1);

3. Reset time delay (elements R2 and Cl); and

4. Output clamping (transistor O2) Bus 11 constitutes the line forreceiving the dc. output voltage representing the condition beingmonitored and bus 12 is coupled to the reference potential (as will bemore fully describd hereinbelow) for establishing a voltage source forthe operation of transistor Q2.

At any input current'below the threshold, transistor Q1 will be of sincethe voltage at its base electrode will be below the required turn-onlevel. Transistor Q2 will then be biased on" by current flow throughresistor R2. Capacitor Cl will have charged to a steady state voltageequal to the base-to-emitter (V of transistor Q2 (typically about 0.60volts). In timing elements such as a capacitor connected to thecollector of 02 would therefore be clamped to a zero state (i.e. fullydischarged).

When the input to the base of O1 is equal to or greater than thethreshold, the voltage divider circuit of zener diode Z1 and adjustableresistor R1 provides a forward bias to 01 which, in turn, shunts thebias current from the base of 02. With 02 now of the timing clementcoupled thereto (as will be more fully described) is released andallowed to charge toward a trigger level to cause tripping of a circuitbreaker.

Upon removal of the input or upon reduction of the input below thedesignated threshold level, 01 turns off and R2 and Cl provide a shorttime delay for resetting the timing element by controlling the time forthe V to reach the forward bias point of Q2. This allows the circuit toremain on" between the adjacent peaks of an ac. current and also formomentary dips below the threshold level.

FIG. 2 shows a simplified version of a static relay employing thecircuit of FIG. 1. In the embodiment of FIG. 2, the individual circuitsare all capable of being operated by a voltage derived from the inputcurrent such as the current transformers CTl CT3, each of which isinductively coupled to the lines of the phases 1-3, respectively. Burdenresistors R develop a voltage at the output of the current transformerswhich is impressed upon associated full-wave bridge rectifier circuitsEl -B respectively. The outputs of the bridge rectifier circuits arecoupled in common across buses 11 and 13 in the manner shown (also noteFIG. 1). The d.c. voltage developed across buses 11 and 13 is thenutilized as a measure of the input magnitude.

The timing controlthreshold is determined by the choice of values forzener diode Z1 and resistor R1. Zener diode Z1 is chosen such that, atits highest tolerance, it is on somewhat below the threshold level.Variable resistor R1 which is provided with slidable tap 20 is then setto provide a forward bias voltage to Q1 when the threshold level isreached.

Indefinite operation will exist only within a narrow band of inputlevels just below the threshold level. Through this region, transistorQ1 progresses from the fully off state to. the fully on state. In thedesign of the present circuit, this region is less than 0.25 percent ofthe threshold level, thus allowing very good precision for the timingcontrol function.

' As a further consideration, the upper resistance portion of resistorR1 should provide current limiting to the base of Q1 at maximum inputlevels.

The transistor 01 is not required to exhibit any special properties andtherefore any ordinary npn transistor may be employed. For a recitfiedsine-wave signal, Q1 will be turned on and then of during eachhalf-cycle of input. Switching will occur at the rising and fallingportions of the sine-wave which correspond to the desired thresholdlevel. Capacitor C1 is thereby discharged to zero during a portion ofeach half-cycle of input above the threshold level.

When Q1 turns off", the voltage on C1 begins to rise-on an exponentialcurve at a rate determined by the time constant of R2 and Cl. Bychoosing the time constant such that the forward bias point of 02 cannot be reached in the time between the half-cycle peaks of the input,the clamp (Q2) will be held off as long as O1 is switching on duringeach half-cycle. Thus, the timing clamp output will remain released aslong as the current input exceeds the threshold level.

For practical situations with signals at an operating frequency ofHertz, a reset time delay of about 20 milliseconds is as fast as isnormally desirable.

It should be noted that R2 must be chosen to provide sufficient basedrive to the base of O2 in order to quickly discharge the timingcapacitor load when reset is initiated after a time delay has beenstarted, but not completed.

This manner of operation completely eliminates any variations betweensingle phase and three phase inputs. It should also be noted that thiscircuit can instantly detect the removal of an overload and initiatetiming reset.

These features show a distinct advantage over present day static relayswhich typically require a smooth dc voltage derived from the peaks ofthe input. Such a circuit, for example, as shown in the above mentionedUS. Pat. No. 3,319,127, requires more components and is more costly thanthe circuit of the present application. Filtered circuits always must becompromised between good single phase to three phase response and thetime lag to sense the removal of an overload. For the formerconsideration, very good filtering is required since the circuitactually responds to the valleys in a fullwave rectified signal as wellas the valleys of the filter ripple. in the latter consideration, theoptimum circuit would have no filtering.

in the circuit of the present invention, both of these functions areseparate and independent in that no filtering is employed to yieldexcellent response regardless of single phase or three phase operationand there is no lag in the time to sense a removal of an overloadcondition as a result of the elimination of the filtering elements whichfurther results in an accompanying significant reduction in cost.

Although there has been described a preferred embodiment of this novelinvention, many variations and modifications will now be apparent tothose skilled in the art. Therefore, this invention is to be limited,not by the specific disclosure herein, but only by the appending claims.

What is claimed is:

1. Static relay means for use in protecting power transmission and/0rdistribution systems against overload conditions comprising:

first means for sensing the current in the system being protected;

second means coupled to said first means for converting the output ofsaid first means into a dc. voltage level respresentative of the currentin the system being protected;

timing means coupled to said second means for generating a predeterminedoutput level after a time interval, which time interval is inverselyproportional to said d.c. level; I

third means coupled to said second means for establishing a constantreference level which is substantially independent of the do outputlevel of said second means;

fourth means having an output coupled to said timing means and beingactivated at its input for resetting said timing means to a zero voltagelevel in the sustained absence of an overload condition in the systembeing monitored;

fifth means having at least one input terminal and an output, said inputterminal coupled to said second means and said output coupled to theinput of said fourth means for activating said fourth means to operatesaid timing means when the output level of said second means is greaterthan a predetermined threshold level (pick-up);

sixth means coupled in common to said third means and the input of saidfourth means for preventing deactivation of said fourth means when theoutput of said second means momentarily falls below said threshold levelto permit continued operation of said timing means once said fourthmeans has been inactivated to enable said timing means to continue itstiming function;

said timing means including at least one capacitor;

said fourth means including first transistor means having first andsecond terminals coupled across said timing means and input means forrendering said transistor means non-conductive when said fourth means isactivated;

said fifth means comprising second transistor means having its outputterminal coupled to said third means and the input of said firsttransistor means and being conductive when said threshold level exceedsthe instantaneous output level of said second means for activating saidfirst transistor means to reset said timing means;

a series connected zener diode means and adjustable resistor meanscoupled across said second means;

said adjustable resistor means including a wiper arm connected directlyto a control electrode at the input of said second transistor means;said zener diode means being adapted to conduct when the level developedby said second means is nearly equal to or greater than said thresholdlevel;

said adjustable resistor means including a portion between said zenerdiode means and the input of said second transistor means, with suchportion having resistance value selected to limit the current drawn bysaid second transistor means to a'safe operating value.

2. The device of claim 1 wherein said sixth means comprises secondcapacitance means for delaying activation of said fourth means until theoutput of said second means drops below said threshold level for apredetermined time interval to prevent resetting of said fourth meansdue to momentary dips in the output level of said second means belowsaid threshold level.

3. The device of claim 1 wherein said system comprises a single phaseline being monitored;

said first means comprising a current sensor inductively coupled to saidline;

said second means comprising a full wave bridge recitifier.

4. The device of claim 1 wherein said system comprises a three phaseline being monitored;

said first means comprising a current sensor for each phase inductivelycoupled to its associated line; said second means comprising a full wavebridge rectifier for each line.

1. Static relay means for use in protecting power transmission and/ordistribution systems against overload conditions comprising: first meansfor sensing the current in the system being protected; second meanscoupled to said first means for converting the output of said firstmeans into a d.c. voltage level respresentative of the current in thesystem being protected; timing means coupled to said second means forgenerating a predetermined output level after a time interval, whichtime interval is inversely proportional to said d.c. level; third meanscoupled to said second means for establishing a constant reference levelwhich is substantially independent of the d.c. output level of saidsecond means; fourth means having an output coupled to said timing meansand being activated at its input for resetting said timing means to azero voltage level in the sustained absence of an overload condition inthe system being monitored; fifth means having at least one inputterminal and an output, said input terminal coupled to said second meansand said output coupled to the input of said fourth means for activatingsaid fourth means to operate said timing means when the output level ofsaid second means is greater than a predetermined threshold level(pick-up); sixth means coupled in common to said third means and theinput of said fourth means for preventing deactivation of said fourthmeans when the output of said second means momentarily falls below saidthreshold level to permit continued operation of said timing means oncesaid fourth means has been inactivated to enable said timing means tocontinue its timing function; said timing means including at least onecapacitor; said fourth means including first transistor means havingfirst and second terminals coupled across said timing means and inputmeans for rendering said transistor means non-conductive when saidfourth means is activated; said fifth means comprising second transistormeans having its output terminal coupled to said third means and theinput of said first transistor means and being conductive when saidthreshold level exceeds the instantaneous output level of said secondmeans for activating said first transistor means to reset said timingmeans; a series connected zener diode means and adjustable resistormeans coupled across said second means; said adjustable resistor meansincluding a wiper arm connected directly to a control elecTrode at theinput of said second transistor means; said zener diode means beingadapted to conduct when the level developed by said second means isnearly equal to or greater than said threshold level; said adjustableresistor means including a portion between said zener diode means andthe input of said second transistor means, with such portion havingresistance value selected to limit the current drawn by said secondtransistor means to a safe operating value.
 2. The device of claim 1wherein said sixth means comprises second capacitance means for delayingactivation of said fourth means until the output of said second meansdrops below said threshold level for a predetermined time interval toprevent resetting of said fourth means due to momentary dips in theoutput level of said second means below said threshold level.
 3. Thedevice of claim 1 wherein said system comprises a single phase linebeing monitored; said first means comprising a current sensorinductively coupled to said line; said second means comprising a fullwave bridge recitifier.
 4. The device of claim 1 wherein said systemcomprises a three phase line being monitored; said first meanscomprising a current sensor for each phase inductively coupled to itsassociated line; said second means comprising a full wave bridgerectifier for each line.